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H8S/2224 Scheda tecnica(PDF) 763 Page - Renesas Technology Corp

Il numero della parte H8S/2224
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  1071 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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H8S/2224 Scheda tecnica(HTML) 763 Page - Renesas Technology Corp

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Section 16 I
2C Bus Interface (IIC) (Option)
Rev. 5.00 Aug 08, 2006 page 677 of 982
REJ09B0054-0500
Table 16.7 I2C Bus Timing (SCL and SDA Output)
Item
Symbol
Output Timing
Unit
Notes
SCL output cycle time
tSCLO
28 tcyc to 256 tcyc
ns
SCL output high pulse width
tSCLHO
0.5 tSCLO
ns
SCL output low pulse width
tSCLLO
0.5 tSCLO
ns
SDA output bus free time
tBUFO
0.5 tSCLO – 1 tcyc
ns
Start condition output hold time
tSTAHO
0.5 tSCLO – 1 tcyc
ns
Retransmission start condition
output setup time
tSTASO
1 tSCLO
ns
Stop condition output setup time
tSTOSO
0.5 tSCLO + 2 tcyc
ns
Data output setup time (master)
tSDASO
1 tSCLLO – 3 tcyc
ns
Data output setup time (slave)*
1
1 tSCLL – 3 tcyc
ns
Data output setup time (slave)*
2
1 tSCLL – (6 tcyc or 12 tcyc)*
3
ns
Data output hold time
tSDAHO
3 tcyc
ns
Figure 27.31
Notes: 1. Not supported by the H8S/2258 Group.
2. Supported only by the H8S/2258 Group.
3. 6 tcyc when IICX is 0, 12 tcyc when IICX is 1.
4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle tcyc, as shown in table 27.22 (H8S/2239 Group)
and table 27.34 (H8S/2238B and H8S/2236B). Note that the I2C bus interface AC timing
specifications will not be met with a system clock frequency of less than 5 MHz.
5. The I2C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for high-
speed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds
the time determined by the input clock of the I2C bus interface, the high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in the table in
table 16.8.



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