H8SSLASH2224 datasheet(764/1071 Pages) RENESAS

764 / 1071 page

Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 678 of 982

REJ09B0054-0500

Table 16.8 Permissible SCL Rise Time (tsr) Values

Time Indication

IICX

tcyc

Indication

2C Bus

Specification

(Max)

φφφφ =

5 MHz*

φφφφ =

8 MHz*

φφφφ =

10 MHz

φφφφ =

16 MHz*

φφφφ =

20 MHz*

7.5 tcyc

Normal mode

1000 ns

937 ns

750 ns

468 ns

375 ns

High-speed

mode

300 ns

17.5 tcyc

Normal mode

1000 ns

875 ns

High-speed

mode

300 ns

Notes: 1. Supported only by the H8S/2239 Group.

2. The H8S/2258 Group is out of operation.

6. The I2C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns

and 300 ns. The I2C bus interface SCL and SDA output timing is prescribed by tcyc, as shown

in table 16.7. However, because of the rise and fall times, the I2C bus interface specifications

may not be satisfied at the maximum transfer rate. Table 16.9 shows output timing calculations

for different operating frequencies, including the worst-case influence of rise and fall times.

The values in the above table will vary depending on the settings of the IICX bit and bits

CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the maximum

transfer rate; therefore, whether or not the I2C bus interface specifications are met must be

determined in accordance with the actual setting conditions.

tBUFO fails to meet the I

2C bus interface specifications at any frequency. The solution is either

(a) to provide coding to secure the necessary interval (approximately 1 µs) between issuance of

a stop condition and issuance of a start condition, or (b) to select devices whose input timing

permits this output timing for use as slave devices connected to the I2C bus.

tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I

2C bus interface

specifications for worst-case calculations of tSr/tSf. Possible solutions that should be

investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and

capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices

whose input timing permits this output timing for use as slave devices connected to the I2C

bus.

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