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H8S/2224 Scheda tecnica(PDF) 765 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 765 Page - Renesas Technology Corp |
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765 / 1071 page ![]() Section 16 I 2C Bus Interface (IIC) (Option) Rev. 5.00 Aug 08, 2006 page 679 of 982 REJ09B0054-0500 Table 16.9 I2C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] Item tcyc Indication tSr/tSf Influence (Max) I 2C Bus Specifi- ation (Min) φφφφ = 5 MHz* 7 φφφφ = 8 MHz* 7 φφφφ = 10 MHz φφφφ = 16 MHz* 3 φφφφ = 20 MHz* 3 tSCLHO 0.5tSCLO (–tSr) Standard mode –1000 4000 4000 4000 4000 4000 4000 High-speed mode –300 600 950 950 950 950 950 tSCLLO 0.5tSCLO (–tSf ) Standard mode –250 4700 4750 4750 4750 4750 4750 High-speed mode –250 1300 1000* 1 1000* 1 1000* 1 1000* 1 1000* 1 tBUFO Standard mode –1000 4700 3800* 1 3875* 1 3900* 1 3938* 1 3950* 1 0.5tSCLO –1tcyc ( –tSr ) High-speed mode –300 1300 750* 1 825* 1 850* 1 888* 1 900* 1 tSTAHO Standard mode –250 4000 4550 4625 4650 4688 4700 0.5tSCLO –1tcyc (–tSf ) High-speed mode –250 600 800 875 900 938 950 tSTASO 1tSCLO (–tSr ) Standard mode –1000 4700 9000 9000 9000 9000 9000 High-speed mode –300 600 2200 2200 2200 2200 2200 tSTOSO Standard mode –1000 4000 4400 4250 4200 4125 4100 0.5tSCLO + 2tcyc (–tSr ) High-speed mode –300 600 1350 1200 1150 1075 1050 Standard mode –1000 250 3100 3325 3400 3513 3550 tSDASO (master) 1tSCLLO* 2 –3tcyc (–tSr ) High-speed mode –300 100 400 625 700 813 850 Standard mode –1000 250 3100 3325 3400 3513 3550 tSDASO (slave)* 4 1tSCLL* 2 –3tcyc (–tSr ) High-speed mode –300 100 400 625 700 813 850 Standard mode –1000 250 — — 2500 — — tSDASO (slave)* 5 1tSCLL* 2 –12tcyc*6 (–tSr ) High-speed mode –300 100 — — –200* 1 —— tSDAHO 3tcyc Standard mode 0 0 600 375 300 188 150 High-speed mode 0 0 600 375 300 188 150 Notes: 1. Does not meet the I 2C bus interface specification. Remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b)adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. The values in the above table will vary depending on the settings of the IICX bit and bits CKS0 to CKS2.Depending on the frequency it may not be possible to achieve the maximum transfer rate; therefore, whether or not the I 2C bus interface specifications are met must be determined in accordance with the actual setting conditions. 2. Calculated using the I 2C bus specification values (standard mode: 4700 ns min; high- speed mode: 1300 ns min). 3. Supported only by the H8S/2239 Group. 4. Not supported by the H8S/2258 Group. 5. Supported only by the H8S/2258 Group. |
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