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H8S/2224 Scheda tecnica(PDF) 817 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 817 Page - Renesas Technology Corp |
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817 / 1071 page ![]() Section 20 Flash Memory (F-ZTAT Version) Rev. 5.00 Aug 08, 2006 page 731 of 982 REJ09B0054-0500 20.5.6 Flash Memory Power Control Register (FLPWCR) FLPWCR enables/disables transition to power-down modes for the flash memory when this LSI enters sub-active mode. Bit Bit Name Initial Value R/W Description 7 PDWND 0 R/W Power Down Disable Enables/disables transition to power-down modes for the flash memory when this LSI enters sub-active mode. 0: Transition to power-down modes for the flash memory enabled. 1: Transition to power-down modes for the flash memory disabled. 6 to 0 — All 0 R Reserved These bits are always read as 0. 20.5.7 Serial Control Register X (SCRX) SCRX performs register access control. Bit Bit Name Initial Value R/W Description 7— 0 R/W Reserved Only 0 should be written to this bit. 6 5 IICX1 IICX0 0 0 R/W R/W I 2C Transfer Select 1, 0 For details, see section 16.3.5, Serial Control Register X (SCRX). 4 IICE 0 R/W I 2C Master Enable For details, see section 16.3.5, Serial Control Register X (SCRX). |
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