H8SSLASH2224 datasheet(820/1071 Pages) RENESAS

820 / 1071 page

Section 20 Flash Memory (F-ZTAT Version)

Rev. 5.00 Aug 08, 2006 page 734 of 982

REJ09B0054-0500

Table 20.4 Boot Mode Operation

Item

Host Operation

Communications Contents

LSI Operation

Boot mode

start

Branches to boot program at reset-start.

Processing Contents

Bit rate

adjustment

Continuously transmits data H'00 at

specified bit rate.

H'00, H'00 ...... H'00

H'00

H'55

· Measures low-level period of receive data

H'00.

· Calculates bit rate and sets it in BRR of

SCI.

· Transmits data H'00 to host as adjustment

end indication.

Transmits data H'AA to host when data

H'55 is received.

Transmits data H'55 when data H'00

is received error-free.

Transmits number of bytes (N) of

programming control program to be

transferred as 2-byte data (low-order

byte following high-order byte)

Receives data H'AA.

Transmits 1-byte of programming

control program (repeated for

N times)

Receives data H'AA.

Transfer of

programming

control

program

Flash memory

erase

Execution of

programming

control program

Boot program initiation

Echobacks the 2-byte data received.

Branches to programming control program

transferred to on-chip RAM and starts

execution.

Echobacks received data to host and also

transfers it to RAM (repeated for N times)

Checks flash memory data, erases all

flash memory blocks in case of written

data existing, and transmits data H'AA to

host. (If erase could not be done,

transmits data H'FF to host and aborts

operation.)

High-order byte and

low-order byte

H'XX

H'AA

Echoback

H'FF

H'AA

Boot program

erase error

Table 20.5 System Clock Frequencies for Which Automatic Adjustment of LSI Bit Rate Is

Possible

System Clock Frequency Range of This LSI

Host Bit Rate

H8S/2258

H8S/2238B, H8S/2238R, H8S/2227

H8S/2239

19,200 bps

8 to 13.5 MHz

8 to 20 MHz

9,600 bps

4 to 13.5 MHz

4 to 20 MHz

4,800 bps

10 to 13.5 MHz

2 to 13.5 MHz

2 to 20 MHz

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