H8SSLASH2224 datasheet(819/1071 Pages) RENESAS

819 / 1071 page

Section 20 Flash Memory (F-ZTAT Version)

Rev. 5.00 Aug 08, 2006 page 733 of 982

REJ09B0054-0500

In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all

flash memory blocks are erased. Boot mode is for use when user program mode is unavailable,

such as the first time on-board programming is performed, or if the program activated in user

program mode is accidentally erased.

2. SCI should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop

bit, and no parity.

3. When the boot program is initiated, the chip measures the low-level period of asynchronous

SCI communication data (H'00) transmitted continuously from the host. The chip then

calculates the bit rate of transmission from the host, and adjusts the SCI bit rate to match that

of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be

pulled up on the board if necessary. After the reset is complete, it takes approximately 100

states before the chip is ready to measure the low-level period.

4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the

completion of bit rate adjustment. The host should confirm that this adjustment end indication

(H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could

not be performed normally, initiate boot mode again by a reset. Depending on the host’s

transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between

the bit rates of the host and the chip. To operate the SCI properly, set the host’s transfer bit rate

and system clock frequency of this LSI within the ranges listed in table 20.5.

5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area

H'FFC000 to H'FFDFFF is the area to which the programming control program is transferred

from the host. The boot program area cannot be used until the execution state in boot mode

switches to the programming control program.

6. Before branching to the programming control program, the chip terminates transfer operations

by SCI (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value

remains set in BRR. Therefore, the programming control program can still use it for transfer of

write data or verify data with the host. The TxD pin is high. The contents of the CPU general

registers are undefined immediately after branching to the programming control program.

These registers must be initialized at the beginning of the programming control program, as the

stack pointer (SP), in particular, is used implicitly in subroutine calls, etc.

7. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting

the FWE pin and mode pins, and executing reset release*. Boot mode is also cleared when a

WDT overflow occurs.

8. All interrupts are disabled during programming or erasing of the flash memory.

Note: * The input signals on the FWE and mode pins must satisfy the mode programming

setup time (tMDS = 200 ns) at the reset release timing.

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