H8SSLASH2224 datasheet(854/1071 Pages) RENESAS

854 / 1071 page

Section 23 Clock Pulse Generator

Rev. 5.00 Aug 08, 2006 page 768 of 982

REJ09B0054-0500

23.1.2

Low-Power Control Register (LPWRCR)

LPWRCR performs down-mode control, selects sampling frequency for eliminating noise,

performs subclock generation control, and specifies multiplication factor.

Bit

Bit Name

Initial Value

R/W

Description

DTON

R/W

Direct Transfer ON Flag

0: When the SLEEP instruction is executed in high-

speed mode or medium-speed mode, operation

shifts to sleep mode, software standby mode, or

watch mode*.

When the SLEEP instruction is executed in sub-

active mode, operation shifts to sub-sleep mode

or watch mode.

1: When the SLEEP instruction is executed in high-

speed mode or medium-speed mode, operation

shifts directly to sub-active mode*, or shifts to

sleep mode or software standby mode.

When the SLEEP instruction is executed in sub-

active mode, operation shifts directly to high-

speed mode, or shifts to sub-sleep mode.

LSON

R/W

Low Speed ON Fag

0: When the SLEEP instruction is executed in high-

speed mode or medium-speed mode, operation

shifts to sleep mode, software standby mode, or

watch mode*.

When the SLEEP instruction is executed in sub-

active mode, operation shifts to watch mode* or

shifts directly to high-speed mode.

Operation shifts to high-speed mode when watch

mode is cancelled.

1: When the SLEEP instruction is executed in high-

speed mode, operation shifts to watch mode or

sub-active mode.

When the SLEEP instruction is executed in sub-

active mode, operation shifts to sub-sleep mode

or watch mode.

Operation shifts to sub-active mode when watch

mode is cancelled.

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