H8SSLASH2224 datasheet(241/1071 Pages) RENESAS

241 / 1071 page

Section 5 Interrupt Controller

Rev. 5.00 Aug 08, 2006 page 155 of 982

REJ09B0054-0500

Internal

address bus

Internal

write signal

CMIEA

CMFA

CMIA

interrupt signal

TCR write cycle by CPU

CMIA exception handling

TCR address

Figure 5.9 Contention between Interrupt Generation and Disabling

5.6.2

Instructions that Disable Interrupts

The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these

instructions are executed, all interrupts including NMI are disabled and the next instruction is

always executed. When the I bit is set by one of these instructions, the new value becomes valid

two states after execution of the instruction ends.

5.6.3

When Interrupts are Disabled

There are times when interrupt acceptance is disabled by the interrupt controller.

The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has

updated the mask level with an LDC, ANDC, ORC, or XORC instruction.

5.6.4

Interrupts during Execution of EEPMOV Instruction

Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.

With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer

is not accepted until the move is completed.

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