H8SSLASH2224 datasheet(240/1071 Pages) RENESAS

240 / 1071 page

Section 5 Interrupt Controller

Rev. 5.00 Aug 08, 2006 page 154 of 982

REJ09B0054-0500

(4) Usage Notes

The SCI and A/D converter interrupt sources are cleared when the DMAC* or DTC reads or

writes the stipulated register. This does not depend on the DTA, DTCE, and DISEL bits.

Note: * Supported only by the H8S/2239 Group.

5.6

Usage Notes

5.6.1

Contention between Interrupt Generation and Disabling

When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes

effective after execution of the instruction.

When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an

interrupt is generated during execution of the instruction, the interrupt concerned will still be

enabled on completion of the instruction, and so interrupt exception handling for that interrupt will

be executed on completion of the instruction. However, if there is an interrupt request of higher

priority than that interrupt, interrupt exception handling will be executed for the higher-priority

interrupt, and the lower-priority interrupt will be ignored.

The same also applies when an interrupt source flag is cleared to 0.

Figure 5.9 shows an example in which the CMIEA bit in the TCR register of the 8-bit timer is

cleared to 0.

The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while

the interrupt is masked.

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