H8SSLASH2224 datasheet(307/1071 Pages) RENESAS

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Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 221 of 982

REJ09B0054-0500

Bit

Bit Name

Initial Value

R/W

Description

DTIE1B

DTIE1A

DTIE0B

DTIE0A

R/W

Data Transfer End Interrupt Enable 1B

Data Transfer End Interrupt Enable 1A

Data Transfer End Interrupt Enable 0B

Data Transfer End Interrupt Enable 0A

These bits enable or disable an interrupt to the

CPU or DTC when transfer ends. If the DTIE bit

is set to 1 when DTE = 0, the DMAC regards

this as indicating the end of a transfer, and

issues a transfer end interrupt request to the

CPU or DTC.

A transfer end interrupt can be canceled either

by clearing the DTIE bit to 0 in the interrupt

handling routine, or by performing processing to

continue transfer by setting the transfer counter

and address register again, and then setting the

DTE bit to 1.

0: Transfer end interrupt is disabled

1: Transfer end interrupt is enabled

(2) Full Address Mode

• DMABCRH

Bit

Bit Name

Initial Value

R/W

Description

FAE1

R/W

Full Address Enable 1

Specifies whether channel 1 is to be used in

short address mode or full address mode.

In full address mode, channels 1A and 1B are

used together as channel 1.

0: Short address mode

1: Full address mode

FAE0

R/W

Full Address Enable 0

Specifies whether channel 0 is to be used in

short address mode or full address mode.

In full address mode, channels 0A and 0B are

used together as channel 0.

0: Short address mode

1: Full address mode

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