H8SSLASH2224 datasheet(309/1071 Pages) RENESAS

309 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 223 of 982

REJ09B0054-0500

Bit

Bit Name

Initial Value

R/W

Description

9DTA0

R/W

Data Transfer Acknowledge 0

These bits enable or disable clearing when

DMA transfer is performed for the internal

interrupt source selected by the DTF3 to DTF0

bits in DMACR of channel 0.

It the DTA0 bit is set to 1 when DTE0 = 1, the

internal interrupt source is cleared automatically

by DMA transfer. When DTE0 = 1 and DTA0 =

1, the internal interrupt source does not issue

an interrupt request to the CPU or DTC.

It the DTA0 bit is cleared to 0 when DTE0 = 1,

the internal interrupt source is not cleared when

a transfer is performed, and can issue an

interrupt request to the CPU or DTC in parallel.

In this case, the interrupt source should be

cleared by the CPU or DTC transfer.

When DTE0 = 0, the internal interrupt source

issues an interrupt request to the CPU or DTC

regardless of the DTA0 bit setting.

The state of the DTME0 bit does not affect the

above operations.

0: Clearing is disabled when DMA transfer is

performed for the selected internal interrupt

source

1: Clearing is enabled when DMA transfer is

performed for the selected internal interrupt

source

8—

R/W

Reserved

This bit can be read from or written to. However,

the write value should always be 0.

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