H8SSLASH2224 datasheet(310/1071 Pages) RENESAS

Il numero della parte	H8S/2224

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

Scroll/Zoom	100%

Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

Logo

310 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 224 of 982

REJ09B0054-0500

• DMABCRL

Bit

Bit Name

Initial Value

R/W

Description

DTME1

R/W

Data Transfer Master Enable 1

Together with the DTE1 bit, this bit controls

enabling or disabling of data transfer on

channel 1. When both the DTME1 bit and DTE1

bit are set to 1, transfer is enabled for channel

If channel 1 is in the middle of a burst mode

transfer when an NMI interrupt is generated, the

DTME1 bit is cleared, the transfer is interrupted,

and bus mastership passes to the CPU. When

the DTME1 bit is subsequently set to 1 again,

the interrupted transfer is resumed. In block

transfer mode, however, the DTME1 bit is not

cleared by an NMI interrupt, and transfer is not

interrupted.

0: Data transfer is disabled

1: Data transfer is enabled

[Clearing conditions]

• When initialization is performed

• When NMI is input in burst mode

• When 0 is written to the DTME1 bit

[Setting condition]

When 1 is written to DTME1 after reading

DTME1 = 0

H8S/2224 Scheda tecnica(PDF) 310 Page - Renesas Technology Corp