H8SSLASH2224 datasheet(320/1071 Pages) RENESAS

320 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 234 of 982

REJ09B0054-0500

8.5

Operation

8.5.1

Transfer Modes

Table 8.4 lists the DMAC transfer modes.

Table 8.4

DMAC Transfer Modes

Transfer Mode

Transfer Source

Remarks

Dual address mode

• 1-byte or 1-word transfer for a

single transfer request

• Specify source and destination

addresses to transfer data in two

bus cycles.

(1) Sequential mode

• Memory address incremented or

decremented by 1 or 2

• Number of transfers: 1 to 65,536

(2) Idle mode

• Memory address fixed

• Number of transfers: 1 to 65,536

(3) Repeat mode

• Memory address incremented or

decremented by 1 or 2

• Continues transfer after sending

number of transfers (1 to 256) and

restoring the initial value

• TPU channel 0 to

5 compare

match/input

capture A interrupt

• SCI transmit-data-

empty interrupt

• SCI receive-data-

full interrupt

• A/D converter

conversion end

interrupt

• External request

Short

address

mode

Single address mode

• 1-byte or 1-word transfer for a

single transfer request

• 1-bus cycle transfer by means of

DACK pin instead of using

address for specifying I/O

• Sequential mode, idle mode, or

repeat mode can be specified

• External request

• Up to 4 channels

can operate

independently

• External request

applies to channel

B only

• Single address

mode applies to

channel B only

H8S/2224 Scheda tecnica(PDF) 320 Page - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 320 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL