H8SSLASH2224 datasheet(319/1071 Pages) RENESAS

319 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 233 of 982

REJ09B0054-0500

priority channel is activated. Transfer requests for other channels are held pending in the DMAC,

and activation is carried out in order of priority.

When DTE = 0 after completion of a transfer, an interrupt request from the selected activation

source is not sent to the DMAC, regardless of the DTA bit setting. In this case, the relevant

interrupt request is sent to the CPU or DTC.

When an interrupt request signal for DMAC activation is also used for an interrupt request to the

CPU or DTC activation (DTA = 0), the interrupt request flag is not cleared by the DMAC.

8.4.2

Activation by External Request

If an external request (

DREQ pin) is specified as a DMAC activation source, the relevant port

should be set to input mode in advance. Level sensing or edge sensing can be used for external

requests.

External request operation in normal mode of short address mode or full address mode is

described below.

When edge sensing is selected, a byte or word is transferred each time a high-to-low transition is

detected on the

DREQ pin. The next data transfer may not be performed if the next edge is input

before data transfer is completed.

When level sensing is selected, the DMAC stands by for a transfer request while the

DREQ pin is

held high. While the

DREQ pin is held low, transfers continue in succession, with the bus being

released each time a byte or word is transferred. If the

DREQ pin goes high in the middle of a

transfer, the transfer is interrupted and the DMAC stands by for a transfer request.

8.4.3

Activation by Auto-Request

Auto-request is activated by register setting only, and transfer continues to the end. With auto-

request activation, cycle steal mode or burst mode can be selected.

In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is

transferred. DMA and CPU cycles are usually repeated alternately. In burst mode, the DMAC

keeps possession of the bus until the end of the transfer so that transfer is performed continuously.

H8S/2224 Scheda tecnica(PDF) 319 Page - Renesas Technology Corp