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7480 Group and 7481 Group User's Manual

1-123

1.14 Serial I/O

HARDWARE

(5)

Notes on Usage of Clock Synchronous Serial I/O

Pay attention to the following notes when clock synchronous serial I/O is selected.

Selecting External Clock as Synchronous Clock

Perform the following operations while the SCLK pin input is HIGH during transmission:

• Write ‘1’ to the transmit enable bit

• Write transmit data to the transmit buffer register

The shift operations of the transmit shift register and the receive shift register are performed while

the synchronous clock is being input to the serial I/O circuit. Stop the synchronous clock with 8

cycles.

Keep the HIGH- and the LOW- width (TWH and TWL) of the pulses used as the external clock

source TWH, TWL [s]

≥ (8/f(XIN) [Hz]). For example, use a frequency of 500 kHz or less (50% duty

cycle) as the external clock source when f(XIN) = 8 MHz.

Set the transmit enable bit to ‘1’ as well as the receive enable bit and the SRDY output enable bit

of the serial I/O control register when the receiver outputs the SRDY signal.

Handling Recovering from Errors Generated

Handling when overrun error is generated

If the next data is stored completely word in the receive shift register before the data transferred

from the receive shift register to the receive buffer register is read through, the overrun error is

generated. At this time, the overrun error flag and the summing error flag of the serial I/O status

buffer register, so that the contents of the receive buffer register remain unaffected. As a result,

if the contents of the receive buffer register are read, the data of the receive shift register is not

transferred to the receive buffer register and becomes invalid.

When the overrun error occurs, clear the overrun error flag to ‘0’ by any of the following operations,

and perform receive preparation again.

• Clear the serial I/O enable bit of the serial I/O control register to ‘0’. (In this case, only the

overrun error flag returns to ‘0’.)

• Clear the receive enable bit of the serial I/O control register to ‘0’.

• Write dummy data into the serial I/O status register.

Referring to Transmit Shift Completion Flag

The transmit shift completion flag changes from ‘1’ to ‘0’ with a delay of 0.5 to 1.5 clocks of the

synchronous clock. Therefore, pay attention to this delay when data transmission is controlled, by

referring to the transmit shift completion flag after the transmit data is written to the transmit buffer

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