7480 datasheet(136/337 Pages) RENESAS

136 / 337 page

7480 Group and 7481 Group User's Manual

1-119

1.14 Serial I/O

HARDWARE

(3)

Operations of Clock Synchronous Serial I/O Reception

Receive Operation

Synchronized with a rising edge of the synchronous clock, a transmitted bit data is received on

the RxD pin, which is stored in the most significant bit (MSB) of the receive shift register.

The contents of the receive shift register are shifted to the low-order direction by one bit every time

a bit data is received, and the next bit data is stored in the MSB. 8-bit data is fully stored in the

receive shift register by repeating this shift operation 8 times.

The completely received 8-bit data stored in the receive shift register is transferred to the receive

buffer register. When the data transfer to the receive buffer register is completed, the receive

buffer full flag of the serial I/O status register is set to ‘1’ (Note).

Note: If the next data is stored completely word in the receive shift register before the data transferred

from the receive shift register to the receive buffer register is read through, the overrun error

is generated. At this time, the overrun error flag and the summing error flag of the serial I/O

status register are set to ‘1’. For the handling in this case, refer to ‘

Handling when overrun

error is generated’ in (5) Notes on Usage of Clock Synchronous Serial I/O.

When the receive buffer register is read, the receive buffer full flag is cleared to ‘0’.

Serial I/O Receive Interrupt

When the data stored completely in the receive shift register is transferred to the receive buffer

Figure 1.14.11 shows the receive operation of clock synchronous serial I/O. The numbers in the

figure corresponds to those of the above-mentioned ‘Receive Operation’.

Figure 1.14.12 shows a receive timing of clock synchronous serial I/O.

7480 Scheda tecnica(PDF) 136 Page - Renesas Technology Corp