PIIX datasheet(101/122 Pages) INTEL

101 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

101

A low speed length babble occurring in a frame followed by a subsequent clearing of the Run/Stop bit will

cause the host controller to lock up from which it can only be restarted by a hardware reset. A length babble

occurs when a device transmits more than the maximum number of bits as specified in the transfer

descriptor. An EOF babble occurs when a device transmits past the frame EOF time point. This condition

does not exist if an EOF babble occurs. If this occurs, the USB host controller can not be restarted, disabling

the system from performing any further USB transactions. A software workaround can prevent a length

babble from being recognized by the host controller for low speed transactions. The software will then be

responsible for detecting the occurrence of a low speed length babble. The host controller detection of low

speed length babble is prevented by setting the Max Packet Length field in each low speed transfer

descriptor to a value greater than the actual number of low speed bytes that can be sent in a frame

(approximately 200). The software will detect the babble by comparing the Actual Length recorded in the

transfer descriptor with a value representing the true Max Packet Length for the endpoint.

Low Speed Length Babble will cause USB Port Disable. If a low speed length babble (see description above)

occurs in a frame, the root hub through which it is attached will be disabled. This is a normal condition for a

babble which exceeds past the EOF point, but is an incorrect condition for length babbles occurring within a

frame. This means the USB port which is disabled will not receive subsequent packets until the port is

reenabled by software. This condition can be corrected using the procedure described above.

A bit stuff error occurs on a USB transaction transferring data from the USB device to the PIIX3. The bit stuff

occurs, but with wrong data value (extra stuff bit was a 1 instead of 0). The data and CRC value are

transferred correctly with no errors. The PIIX3 will detect the bit stuff error, discard the data, clear the Active

bit, and set the Bit Stuff Error bit. The PIIX3 will incorrectly acknowledge (ACK) the transfer to the USB

device, will not update the queue header, and does not set the Stall bit. This condition can occur if the USB

device inserts the wrong stuff bit or if noise on the USB subsystem causes only this single bit to change. This

means the USB device’s data toggle bit will become out of “sync” with the host schedule’s data toggle bit.

This will effectively result in a stalled USB device endpoint, halting data transfers to or from the USB device.

The USB host controller software (UHCI drivers) must check for a set Bit Stuff Error bit with no corresponding

Stall bit set or simply check for an inactive transfer descriptor with a non-zero status field. When this condition

is detected, the USB host controller software must stall the device endpoint and reinitialize the USB device.

If PCI latency at the end of a USB transaction pushes the status update beyond the start of the next frame,

then the Babble, NAK, and Timeout error condition detection may be delayed by one frame. There is no

visual effect on functionality of performance. An alternative method of status monitoring in software is

necessary for immediate detection. Each of the 3 conditions can be detected as described below.

NAK Status: If the Active bit is set then no patch is needed as the transaction will be automatically

retried.

Babble Status: If Error Count <> 0, which precludes CRC/Timeout conditions and no other status bits

are set other than the Stalled bit, precluding Bit Stuff and Data Buffer conditions, then treat this Babble

condition like a Stall.

Timeout Status: If the Stalled bit is set and Error Count = 0 AND either there is no Data Buffer error or

there is no Bitstuff error, then treat this condition as a CRC/Timeout error.

More information concerning the PIIX3 USB Host Controller operation can be found in the Universal Host

Controller Interface Design Guide, available from Intel Literature Center as document number 297650.

PIIX Scheda tecnica(PDF) 101 Page - Intel Corporation

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