PIIX datasheet(104/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

104

3.8.1.

PROGRAMMING THE ICWs/OCWs

The Interrupt Controller accepts two types of command words generated by the CPU or bus master:

1. Initialization Command Words (ICWs): Before normal operation can begin, each Interrupt Controller in

the system must be initialized. In the 82C59, this is a two to four byte sequence. However, for the PIIX, each

controller must be initialized with a four byte sequence. This four byte sequence is required to configure the

interrupt controller correctly for the PIIX/PIIX3 implementation. This implementation is ISA-compatible. The

four initialization command words are referred to by their acronyms: ICW1, ICW2, ICW3, and ICW4. The base

address for each interrupt controller is a fixed location in the I/O memory space, at 0020h for CNTRL-1 and at

00A0h for CNTRL-2.

An I/O write to the CNTRL-1 or CNTRL-2 base address with data bit 4 equal to 1 is interpreted as ICW1. For

PIIX-based ISA systems, three I/O writes to "base address + 1" (021h for CNTRL-1 and 0A1h for CNTRL-2)

must follow the ICW1. The first write to "base address + 1" (021h/0A1h) performs ICW2, the second write

performs ICW3, and the third write performs ICW4.

2. Operation Command Words (OCWs): These are the command words that dynamically reprogram the

interrupt controller to operate in various interrupt modes. Any interrupt lines can be masked by writing an

OCW1. A 1 written in any bit of this command word masks incoming interrupt requests on the corresponding

IRQx line. OCW2 is used to control the rotation of interrupt priorities when operating in the rotating priority

mode and to control the End of Interrupt (EOI) function of the controller. OCW3 set up reads of the ISR and

IRR, enable/disables the Special Mask Mode (SMM), and sets up the interrupt controller in polled interrupt

mode. The OCWs can be written to the Interrupt Controller any time after initialization.

3.8.2.

EDGE AND LEVEL TRIGGERED MODE

In ISA systems this mode is programmed using bit 3 in ICW1. With PIIX/PIIX3 this bit is disabled and a new

control Registers ELCR1 and ELCR2. The default programming is equivalent to programming the LTIM bit

(ICW1 bit 3) to a 0 (all interrupts selected for edge triggered mode). Note, that IRQ0, 1, 2, 8#, and 13 can not

be programmed for level sensitive mode and can not be modified by software.

If an ELCR bit = 0, an interrupt request is recognized by a low to high transition on the corresponding IRQx

input. The IRQ input can remain high without generating another interrupt.

If an ELCR bit = 1, an interrupt request is recognized by a high level on the corresponding IRQ input and

there is no need for an edge detection. The interrupt request must be removed before the EOI command is

issued to prevent a second interrupt from occurring.

In both the edge and level triggered modes, the IRQ inputs must remain asserted until the cycle starts (PCI

INTA cycle); with FRAME# and IRDY# both asserted. After that, the IRQ may be removed. If the IRQ input

goes inactive before this time, a default IRQ7 occurs when the CPU acknowledges the interrupt. This can be

a useful safeguard for detecting interrupts caused by spurious noise glitches on the IRQ inputs. To implement

this feature, the IRQ7 routine is used for "clean up" simply executing a return instruction, thus ignoring the

interrupt. If IRQ7 is needed for other purposes, a default IRQ7 can still be detected by reading the ISR. A

normal IRQ7 interrupt sets the corresponding ISR bit. A default IRQ7 does not set this bit. However, If a

default IRQ7 routine occurs during a normal IRQ7 routine, the ISR remains set. In this case, it is necessary to

keep track of whether or not the IRQ7 routine was previously entered. If another IRQ7 occurs, it is a default.

3.8.3.

INTERRUPT STEERING

The PIIX/PIIX3 can be programmed to allow four PCI programmable interrupts (PIRQ[D:A]#) to be internally

routed to one of 11 interrupts (IRQ[15,14,12:9,7:3]) using the PIRQx Route Control Register. PCLK is used to

synchronize the PIRQx# inputs. The assignment is programmable through the PIRQx Route Control

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