PIIX datasheet(105/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

105

registers. One or more PIRQx# lines can be routed to the same IRQx input. If interrupt steering is not

required, the Route Registers can be programmed to disable steering.

For the PIIX3, the Universal Serial Bus (USB) Module interrupt is hardwired to the PIRQD# signal. When the

USB is enabled, the USB Host Controller in PIIX3 uses the PIRQD# input to the internal interrupt controller. If

an IOAPIC is used, the USB outputs interrupts on PIRQD# to the external IOAPIC. When the USB function is

disabled, other PCI devices can use the PIRQD# input.

The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts on a PCI Board to

share a single line across the connector. When a PIRQx# is routed to a specified IRQ line, the software must

change the IRQ’s corresponding ELCR bit to level sensitive mode. Note, that this means that the selected

IRQ can no longer be used by an ISA device, unless that ISA device can respond as an active low level

sensitive interrupt.

The 82371FB PIIX supports up to two programmable interrupts (MIRQ[1:0]; intended for use with

motherboard devices) to be routed to one of the 11 interupts (IRQ[15,14,12:9,7:3]) using the MBIRQx Route

Control Register. The routing is accomplished in the same manner as for the PIRQx# inputs, except that the

interrupts are active high. Two MIRQx lines may be routed to the same IRQx input. If interrupt steering is not

required, the MBIRQx registers can be programmed to disable routing. Note that only one motherboard

interrupt (MIRQ0) is available on PIIX3.

For the 82371FB PIIX , when more than one MIRQ line is routed to an IRQ input, the software must change

the IRQ’s corresponding ELCR bit to level sensitive mode. Interrupt sharing for motherboard devices must be

evaluated for the particular combination of devices under consideration. The IRQ selected bit MBIRQx[3:0]

can no longer be used by an ISA device, unless that ISA device can respond as an active high level sensitive

interrupt.

IRQ[15:9,8#,7:1]

PIRQ[A:C]#

MIRQ0

051909_3.drw

Internal

82C59s

PIIX/PIIX3

Interrupt

Steering

Logic

MIRQ1

(PIIX Only)

(PIIX and PIIX3)

PIRQD#

Universal

Serial Bus

Module

(PIIX3 Only)

Interrupt

051909

Note: MIRQ1 is only availabe on PIIX. MIRQ0 is available on both PIIX and PIIX3.

Figure 8. Interrupt Steering

3.9.

Stand-Alone IOAPIC Support (PIIX3)

The PIIX3 supports a stand-alone IOAPIC device on the ISA X-Bus. The PIIX3 provides a chip select signal

(APICCS#) for the IOAPIC. It also provides handshake signals to maintain buffer coherency in the IOAPIC

environment.

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