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PIIX Scheda tecnica(PDF) 102 Page - Intel Corporation

Il numero della parte PIIX
Spiegazioni elettronici  82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
PDF  122 Pages
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Produttore elettronici  INTEL [Intel Corporation]
Homepage  http://www.intel.com
Logo INTEL - Intel Corporation

PIIX Scheda tecnica(HTML) 102 Page - Intel Corporation

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82371FB (PIIX) AND 82371SB (PIIX3)
E
102
Universal Serial
Bus D river (USBD)
Universal Host
Controller Driver (HCD)
PIIX3
Universal Host Controller (HC)
USB D evice
USB
usb_blk. drw
Hardware
Client Softw are
System
Software
USB Device
USB
Universal Host
Controller Interface
(UHCI)
USB_BLK
Figure 6. USB System Conceptual View
3.7.
Interval Timer
The PIIX/PIIX3 contains three counters that are equivalent to those found in the 82C54 programmable
interval timer. The three counters are contained in one PIIX/PIIX3 timer unit, referred to as Timer-1. Each
counter output provides a key system function. Counter 0 is connected to interrupt controller IRQ0 and
provides a system timer interrupt for a time-of-day, diskette time-out, or other system timing functions.
Counter 1 generates a refresh request signal and Counter 2 generates the tone for the speaker. The
14.31818 MHz counters normally use OSC as a clock source.
Counter 0, System Timer
This counter functions as the system timer by controlling the state of IRQ0 and is typically programmed for
mode 3 operation. The counter produces a square wave with a period equal to the product of the counter
period (838 ns) and the initial count value. The counter loads the initial count value one counter period after
software writes the count value to the counter I/O address. The counter initially asserts IRQ0 and decrements
the count value by two each counter period. The counter negates IRQ0 when the count value reaches 0. It
then reloads the initial count value and again decrements the initial count value by two each counter period.
The counter then asserts IRQ0 when the count value reaches 0, reloads the initial count value, and repeats
the cycle, alternately asserting and negating IRQ0.



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