AD6673 datasheet(42/46 Pages) AD

42 / 46 page

Data Sheet

AD6673

Rev. C | Page 41 of 45

Reg

Addr

(Hex)

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Notes

0x3A

SYNCINB±/

SYSREF±

CTRL

Realign on

SYNCINB±;

for

Subclass 1

only: 0 =

normal

mode;

1 = realign

lanes on

every

active

SYNCINB±

Realign

SYSREF±;

for

Subclass

1 only: 0

= normal

mode;

1 =

realign

lanes on

every

active

SYSREF±;

use with

one-shot

SYSREF in

Subclass 1

mode

SYSREF±

mode;

0 =

continuous

reset clock

dividers;

1 = sync on

SYSREF±

rising edge

only

SYSREF±

enable;

0 =

disabled;

1 =

enabled

NOTE: This

bit will

self-clear

after

SYSREF if

SYSREF±

mode = 1

Enable

internal

SYSREF±

buffer;

0 = buffer

disabled,

external

SYSREF±

ignored;

1 = buffer

enabled,

use

external

SYSREF±

signal

0x00

0x3C

NSR CTRL

Bandwidth

mode;

0 = 22%;

1 = 33%

NSR enable

0x00

0x3E

NSR tuning

Noise shaped requantizer tuning frequency;

selects the center frequency of the noise transfer function (NTF);

57 possible tuning words (TW) exist; each step is 0.5% of the ADC sample rate

0x1C

0x40

DCC CTRL

Freeze dc

correction;

0 =

calculate;

1 = freeze

value

DC correction bandwidth select;

correction bandwidth is 2387.32 Hz/reg value;

there are 14 possible values;

0000 = 2387.32 Hz;

0001 = 1193.66 Hz;

1101 = 0.29 Hz

Enable

DCC

0x00

0x41

DCC value

LSB

DC Correction Value[7:0]

0x00

0x42

DCC value

MSB

DC Correction Value[15:8]

0x00

0x45

Fast detect

control

function;

0 = fast

detect;

1 =

overrange

Force

FDA/FDB

pins;

0 =

normal

function;

1 = force

to value

Force

value of

FDA/FDB

pins;

if force

pins is true,

this value

is output

on FD pins

Enable fast

detect

output

0x00

0x47

FD upper

threshold

Fast Detect Upper Threshold[7:0]

0x00

0x48

FD upper

threshold

Fast Detect Upper Threshold[14:8]

0x00

0x49

FD lower

threshold

Fast Detect Lower Threshold[7:0]

0x00

0x4A

FD lower

threshold

Fast Detect Lower Threshold[14:8]

0x00

0x4B

FD dwell

time

Fast Detect Dwell Time[7:0]

0x00

0x4C

FD dwell

time

Fast Detect Dwell Time[15:8]

0x00

0x5E

204B quick

config

Quick configuration register, always reads back 0x00;

0x11 = M = 1, L = 1; one converter, one lane; second converter is not automatically powered down;

0x12 = M = 1, L = 2; one converter, two lanes; second converter is not automatically powered down;

0x21 = M = 2, L = 1; two converters, one lane;

0x22 = M = 2, L = 2; two converters, two lanes

0x00

Always

reads

back

0x00

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