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AD6673

Data Sheet

Rev. C | Page 30 of 45

Verify FCHK, Checksum of JESD204B Interface Parameters

The JESD204B parameters can be verified through the checksum

value [FCHK] of the JESD204B interface parameters. Each lane has

an FCHK value associated with it. The FCHK value is transmitted

during the ILAS second multiframe and can be read from the

internal registers.

The checksum value is the modulo 256 sum of the parameters

listed in the No. column of Table 12. The checksum is calculated

by adding the parameter fields before they are packed into the

octets shown in Table 12.

The FCHK for the lane configuration for data coming out of

Lane 0 can be read from Register 0x78. Similarly, the FCHK for

the lane configuration for data coming out of Lane 1 can be read

from Register 0x79.

Table 12. JESD204B Configuration Table Used in ILAS and

CHKSUM Calculation

No.

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

DID[7:0]

BID[3:0]

LID[4:0]

SCR

L[4:0]

F[7:0]

K[4:0]

M[7:0]

CS[1:0]

N[4:0]

SUBCLASS[2:0]

N’[4:0]

JESDV[2:0]

S[4:0]

CF[4:0]

Additional Digital Output Configuration Options

Other data format controls include the following:

•

Invert the polarity of the serial output data: Register 0x60,

Bit 1.

•

ADC data format (offset binary, twos complement):

•

Options for interpreting SYSREF± and SYNCINB± signals in

•

Option to remap converter and lane assignments,

simplified block diagram.

Reenable Lanes After Configuration

After modifying the JESD204B link parameters, enable the link

so that the synchronization process can begin. This is accomplished

by writing Logic 0 to Register 0x5F, Bit 0.

CONVERTER A

CONVERTER B

INPUT

CONVERTER A

INPUT

SYSREF

SYNCINB

CONVERTER B

SAMPLE

CONVERTER A

SAMPLE

AD6673 DUAL IF RECEIVER

LANE 0

LANE 1

SERDOUT0

SERDOUT1

LANE 1

LANE 0

PRIMARY CONVERTER

INPUT [0]

PRIMARY LANE

OUTPUT [0]

PRIMARY CONVERTER

INPUT [0]

PRIMARY LANE

OUTPUT [0]

JESD204B LANE CONTROL

(M = 1, 2; L = 1, 2)

LANE MUX

(SPI REGISTER

MAPPING: 0x82,0x83)

SECONDARY CONVERTER

INPUT [1]

SECONDARY LANE

OUTPUT [1]

SECONDARY CONVERTER

INPUT [1]

SECONDARY LANE

OUTPUT [1]

JESD204B LANE CONTROL

(M = 1, 2; L = 1, 2)

Figure 49. AD6673 Transmit Link Simplified Block Diagram

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