AD6673 datasheet(29/46 Pages) AD

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AD6673

Data Sheet

Rev. C | Page 28 of 45

Clock Adjustment Register Writes

Perform the clock adjustment writes in the following order:

1. Set Register 0xEE to 0x81.

2. Set Register 0xEF to 0x81.

3. Set Register 0xEE to 0x82.

4. Set Register 0xEF to 0x82.

5. Set Register 0xEE to 0x83.

6. Set Register 0xEF to 0x83.

7. Set Register 0xEE to 0x84.

8. Set Register 0xEF to 0x84.

9. Set Register 0xEE to 0x85.

10. Set Register 0xEF to 0x85.

11. Set Register 0xEE to 0x86.

12. Set Register 0xEF to 0x86.

13. Set Register 0xEE to 0x87.

14. Set Register 0xEF to 0x87.

JESD204B Synchronization Details

The AD6673 supports JESD204B Subclass 0 and Subclass 1, and

establishes synchronization of the link through one or two control

signals, SYNC and, for Subclass 1, SYSREF, and a common device

clock. SYSREF and SYNC are common to all converter devices

for alignment purposes at the system level.

The synchronization process is accomplished over three phases:

code group synchronization (CGS), initial lane alignment sequence

(ILAS), and data transmission. If scrambling is enabled, the bits are

not actually scrambled until the data transmission phase, and

the CGS phase and ILAS phase do not use scrambling.

CGS Phase

In the CGS phase, the JESD204B transmit block transmits

/K28.5/ characters. The receiver (external logic device) must

locate K28.5 characters in its input data stream using clock and

data recovery (CDR) techniques.

When in Subclass 1 mode, the receiver locks on to the K28.5

characters. Once detected, the receiver initiates a SYSREF edge

so that the AD6673 transmit data establishes an LMFC internally.

The SYSREF edge also resets any sampling edges within the ADC

to align sampling instances to the LMFC. This is important to

maintain synchronization across multiple devices.

At the internal clock of the next receiver, if Subclass 0, or at the

LMFC boundary of the next receiver, if Subclass 1, the receiver

or logic device deasserts the SYNC~ signal (SYNCINB± goes

high), and the transmitter block begins the ILAS phase.

ILAS Phase

In the ILAS phase, the transmitter sends out a known pattern,

and the receiver aligns all lanes of the link and verifies the

parameters of the link.

The ILAS phase begins after SYNC~ has been deasserted (goes

high). If Subclass 0, the transmitter begins ILAS at the internal

clock of the next transmitter. If Subclass 1, at the LMFC bound-

ary of the next transmitter, the transmit block begins to

transmit four multiframes. Dummy samples are inserted between

the required characters so that full multiframes are transmitted.

The four multiframes include the following:

•

Multiframe 1: Begins with an /R/ character [K28.0] and

ends with an /A/ character [K28.3].

•

Multiframe 2: Begins with an /R/ character followed by a /Q/

[K28.4] character, followed by link configuration parameters

over 14 configuration octets (see Table 10), and ends with

an /A/ character. Many of the values of the parameters are

of the notation of the value – 1.

•

Multiframe 3: Is the same as Multiframe 1.

•

Multiframe 4: Is the same as Multiframe 1.

Data Transmission Phase

In the data transmission phase, frame alignment is monitored

with control characters. Character replacement is used at the

end of frames. Character replacement in the transmitter occurs

in the following instances:

•

If scrambling is disabled and the last octet of the frame or

multiframe equals the octet value of the previous frame.

•

If scrambling is enabled and the last octet of the multiframe is

equal to 0x7C, or the last octet of a frame is equal to 0xFC.

Table 10. Fourteen Configuration Octets of the ILAS Phase

No.

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

DID[7:0]

BID[3:0]

LID[4:0]

SCR

L[4:0]

F[7:0]

K[4:0]

M[7:0]

CS[1:0]

N[4:0]

SUBCLASS[2:0]

N’[4:0]

JESDV[2:0]

S[4:0]

CF[4:0]

Reserved, Don’t Care

FCHK[7:0]

Link Setup Parameters

The following sections demonstrate how to configure the

AD6673 JESD204B interface paremeters. These details are a

subset of the setup details provided in the Synchronization

section. The steps to configure the output include the following:

1. Disable the lanes before changing the configuration.

2. Select the quick configuration option.

3. Configure the detailed options.

4. Verify FCHK, the checksum of the JESD204B interface

parameters.

5. Set additional digital output configuration options.

6. Reenable the lane(s).

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