AD6673 datasheet(28/46 Pages) AD

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Data Sheet

AD6673

Rev. C | Page 27 of 45

SYNCHRONIZATION

The AD6673 requires internal synchronization to process the

ADC data and produce a JESD204B output. To accommodate

extreme temperature changes and inconsistent power-up

conditions that may occur, the timing of these circuits requires

an additional margin. To increase the timing margin, a

procedure is required to maintain internal timing

synchronization and JESD204B link quality.

There are four specific cases to consider: JESD204B Subclass 0

or Subclass 1 operation, and Nyquist or harmonic clocking.

Harmonic clocking uses an input clock, where the AD6673

internal clock divider can be set to divide by a multiple of

between 2 and 8 of the ADC sample rate (using Register 0x0B).

See Table 14 for a description of how the JESD204B link modes

of operation are configured using Register 0x3A.

Subclass 0 and Nyquist Input Clock

For Subclass 0 and Nyquist input clock (deterministic latency is

not required and an external SYSREF signal is not used),

1. Apply power to the AD6673. Allow the voltages and clocks

to stabilize.

2. Apply a soft reset by writing 0x3C to Register 0x00.

3. Wait at least 500 µs.

4. Set Register 0xEE and Register 0xEF to 0x80.

5. Configure the AD6673 as desired, including the JESD204B

parameters. Configure the link setup parameters (see the

Link Setup Parameters section).

6. Establish an internal local multiframe clock (LMFC)

within the AD6673 by writing 0xFF to Register 0xF3.

7. Wait at least six LMFCs.

8. Perform the clock adjustment register writes (see the Clock

Adjustment Register Writes section).

9. Wait at least six LMFCs.

10. Enable the JESD204B receiver, and initiate a link.

Subclass 1 and Nyquist Input Clock

For Subclass 1 and the Nyquist input clock (when deterministic

latency is required and an external SYSREF is used),

1. Apply power to the AD6673. Allow the voltages and clocks

to stabilize.

2. Apply a soft reset by writing 0x3C to Register 0x00.

3. Wait at least 500 µs.

4. Set Register 0xEE and Register 0xEF to 0x80.

5. Configure the AD6673 as desired including the JESD204B

parameters. Configure the link setup parameters (see the

Link Setup Parameters section).

6. Force an internal alignment within the AD6673 by writing

0xFF to Register 0xF3.

7. Wait at least six LMFCs.

8. Establish a LMFC within the AD6673 by providing a

SYSREF signal.

9. Perform the clock adjustment register writes (see the Clock

Adjustment Register Writes section).

10. Wait at least six LMFCs.

11. Enable the JESD204B receiver, and initiate a link.

Subclass 0 and Harmonic Input Clock

For Subclass 0 and the harmonic input clock,

1. Apply power to the AD6673. Allow the voltages and clocks

to stabilize.

2. Assert a power-down by either using the PDWN input or

by setting Register 0x08 to 0x05.

3. Configure the proper clock divide setting in Register 0x0B.

Commit the clock divide setting by writing 0x01 to

4. Set Register 0xEE and Register 0xEF to 0x80.

5. Configure the AD6673 as desired including the JESD204B

parameters. Configure the link setup parameters (see the

Link Setup Parameters section).

6. Deassert the power-down, and wait at least 250 ms.

7. Force an internal alignment within the AD6673 by writing

0xFF to Register 0xF3.

8. Wait at least six LMFCs.

9. Perform the clock adjustment register writes (see the Clock

Adjustment Register Writes section).

10. Wait at least six LMFCs.

11. Enable the JESD204B receiver, and initiate a link.

Subclass 1 and Harmonic Input Clock

For Subclass 1 and the harmonic input clock,

1. Apply power to the AD6673. Allow the voltages and clocks

to stabilize.

2. Assert a power-down by either using the PDWN input or

by setting Register 0x08 to 0x05.

3. Configure the proper clock divide setting in Register 0x0B.

Commit the clock divide setting by writing 0x01 to

4. Set Register 0xEE and Register 0xEF to 0x80.

5. Configure the AD6673 as desired including the JESD204B

parameters. Configure the link setup parameters (see the

Link Setup Parameters section).

6. Deassert the power-down, and wait at least 250 ms.

7. Force an internal alignment within the AD6673 by writing

0xFF to Register 0xF3.

8. Wait at least six LMFCs.

9. Set the LMFC using the SYSREF signal for JESD204B

Subclass 1 operation.

10. Perform the clock adjustment register writes (see the Clock

Adjustment Register Writes section).

11. Enable the JESD204B receiver, and initiate a link.

12. Wait at least six LMFCs.

13. Bring the JESD204B receiver out of reset.

If the AD6673 has been configured for continuous SYSREF± mode

of operation using Register 0x3A, Bit 2 = 1, it is important to

disable the internal SYSREF± buffer by setting Register 0x3A,

Bit 0 = 0, to remove the impact of external false triggers that

affects the digital path.

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