AD6673 datasheet(45/46 Pages) AD

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AD6673

Data Sheet

Rev. C | Page 44 of 45

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting system level design and layout of the AD6673, it

is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections and

layout requirements needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD6673, use two separate 1.8 V

power supplies. The power supply for AVDD can be isolated and

for DVDD and DRVDD it can be tied together, in which case

isolation between DVDD and DRVDD is required. Isolation can

be achieved using a ferrite bead or an inductor of approximately

1 µH. An unfiltered switching regulator is not recommended

for the DRVDD supply as it impacts the performance of the

JESD204B serial transmission lines and may result in link

problems. Alternately, the JESD204B PHY power (DRVDD)

and analog (AVDD) supplies can be tied together, and a

separate supply can be used for the digital outputs (DVDD).

The designer can employ several different decoupling capacitors

to cover both high and low frequencies. Locate these capacitors

close to the point of entry at the PC board level and close to the

pins of the part with minimal trace length. Each power supply

domain must have local high frequency decoupling capacitors.

This is especially important for DRVDD and AVDD to

maintain analog performance.

When using the AD6673, a single PCB ground plane is sufficient.

With proper decoupling and smart partitioning of the PCB analog,

digital, and clock sections, optimum performance is easily

achieved.

Exposed Paddle Thermal Heat Slug Recommendations

It is mandatory that the exposed paddle on the underside of the

ADC be connected to analog ground (AGND) to achieve the

best electrical and thermal performance. Mate a continuous,

exposed (no solder mask) copper plane on the PCB to the

AD6673 exposed paddle, Pin 0.

The copper plane must have several vias to achieve the lowest

possible resistive thermal path for heat dissipation to flow

through the bottom of the PCB. Fill or plug these vias with

nonconductive epoxy.

To maximize the coverage and adhesion between the ADC and

the PCB, overlay a silkscreen to partition the continuous plane

on the PCB into several uniform sections. This provides several tie

points between the ADC and the PCB during the reflow process.

Using one continuous plane with no partitions guarantees only

one tie point between the ADC and the PCB. See the evaluation

board for a PCB layout example. For detailed information about

the packaging and PCB layout of chip scale packages, refer to

the AN-772 Application Note, A Design and Manufacturing

Guide for the Lead Frame Chip Scale Package (LFCSP).

VCM

Decouple the VCM pin to ground with a 0.1 μF capacitor, as

shown in Figure 29. For optimal channel-to-channel isolation,

include a 33 Ω resistor between the AD6673 VCM pin and the

Channel A analog input network connection, as well as between

the AD6673 VCM pin and the Channel B analog input network

connection.

SPI Port

When the full dynamic performance of the converter is required,

do not activate the SPI port during periods. Because the SCLK,

CS, and SDIO signals are typically asynchronous to the ADC clock,

noise from these signals can degrade converter performance. If

the on-board SPI bus is used for other devices, it may be necessary

to provide buffers between this bus and the AD6673 to keep

these signals from transitioning at the converter input pins

during critical sampling periods.

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