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AD6673

Data Sheet

Rev. C | Page 10 of 45

TIMING SPECIFICATIONS

Table 5.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

SPI TIMING REQUIREMENTS (See Figure 56)

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

CLK

Period of the SCLK

Setup time between CS and SCLK

Hold time between CS and SCLK

HIGH

Minimum period that SCLK should be in a logic high state

LOW

Minimum period that SCLK should be in a logic low state

EN_SDIO

Time required for the SDIO pin to switch from an input to an

output relative to the SCLK falling edge (not shown in figures)

DIS_SDIO

Time required for the SDIO pin to switch from an output to an

input relative to the SCLK rising edge (not shown in figures)

SPI_RST

Time required after hard or soft reset until SPI access is available

(not shown in figures)

500

µs

Timing Diagrams

N – 36

N – 35

N – 34

N – 33

N – 1

N + 1

SAMPLE N

ANALOG

INPUT

SIGNAL

CLK–

CLK+

CLK–

CLK+

SERDOUT1±

SERDOUT0±

SAMPLE N – 36

ENCODED INTO 2

8b/10b SYMBOLS

SAMPLE N – 35

ENCODED INTO 2

8b/10b SYMBOLS

SAMPLE N – 34

ENCODED INTO 2

8b/10b SYMBOLS

Figure 2. Data Output Timing

tREFS

tREFH

tREFHRF

NOTES

1. CLOCK INPUT IS EITHER RFCLK OR CLK±, NOT BOTH.

CLK+

CLK–

SYSREF+

SYSREF–

RFCLK

SYSREF+

SYSREF–

tREFSRF

Figure 3. SYSREF± Setup and Hold Timing

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