AD6673 datasheet(22/46 Pages) AD

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Data Sheet

AD6673

Rev. C | Page 21 of 45

100Ω

0.1µF

240Ω

PECL DRIVER

50kΩ

CLK–

CLK+

CLOCK

INPUT

CLOCK

INPUT

AD95xx

ADC

Figure 35. Differential PECL Sample Clock (Up to 625 MHz)

Analog Devices also offers LVDS clock drivers with excellent

jitter performance. A typical circuit is shown in Figure 36 and

uses LVDS drivers such as the AD9510, AD9511, AD9512,

AD9513, AD9514, AD9515, AD9516-0, AD9516-1, AD9516-2,

AD9516-3, AD9516-4, AD9516-5, AD9517-0, AD9517-1,

AD9517-2, AD9517-3, AD9517-4, AD9518-0, AD9518-1,

AD9518-2, AD9518-3, AD9518-4, AD9520-0, AD9520-1,

AD9520-2, AD9520-3, AD9520-4, AD9520-5, AD9522-0,

AD9522-1, AD9522-2, AD9522-3, AD9522-4, AD9522-5,

AD9523, and AD9524.

100Ω

0.1µF

50kΩ

CLK–

CLK+

CLOCK

INPUT

CLOCK

INPUT

AD95xx

LVDS DRIVER

ADC

Figure 36. Differential LVDS Sample Clock (Up to 625 MHz)

RF Clock Input Options

The AD6673 RF clock input supports a single-ended clock

between 625 GHz to 1.5 GHz. The equivalent RF clock input

circuit is shown in Figure 37. The input is self biased to 0.9 V and is

typically ac-coupled. The input has a typical input impedance of

10 kΩ in parallel with 1 pF at the RFCLK pin.

BIAS

CONTROL

10kΩ

RFCLK

INTERNAL

CLOCK DRIVER

1pF

Figure 37. Equivalent RF Clock Input Circuit

It is recommended that the RF clock input of the AD6673 be

driven with a PECL or sine wave signal with a minimum signal

amplitude of 600 mV peak to peak. Regardless of the type of

signal being used, clock source jitter is of the most concern, as

described in the Jitter Considerations section. Figure 38 shows the

preferred method of clocking when using the RF clock input on

the AD6673. It is recommended that a 50 Ω transmission line

be used to route the clock signal to the RF clock input of the

AD6673 due to the high frequency nature of the signal and

terminate the transmission line close to the RF clock input.

RFCLK

ADC

50Ω Tx LINE

RF CLOCK

INPUT

0.1µF

50Ω

Figure 38. Typical RF Clock Input Circuit

Figure 39 shows the RF clock input of the AD6673 being driven

from the LVPECL outputs of the AD9515. The differential

LVPECL output signal from the AD9515 is converted to a single-

ended signal using an RF balun or RF transformer. The RF balun

configuration is recommended for clock frequencies associated

with the RF clock input.

0.1µF

LVPECL

DRIVER

AD9515

127Ω

VDD

82.5Ω

127Ω

82.5Ω

CLOCK INPUT

RFCLK

ADC

50Ω Tx LINE

0.1µF

50Ω

Figure 39. Differential PECL RF Clock Input Circuit

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