AD6673 datasheet(10/46 Pages) AD

10 / 46 page

Data Sheet

AD6673

Rev. C | Page 9 of 45

Parameter

Temperature

Min

Typ

Max

Unit

Low Level Output Voltage (V

OL)

Full

OL = 1.6 mA

Full

0.2

OL = 50 µA

Full

0.05

1 Pull-up.

2 Pull-down.

SWITCHING SPECIFICATIONS

Table 4.

Parameter

Symbol

Temperature

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Conversion Rate1

Full

250

MSPS

SYSREF± Setup Time to Rising Edge CLK±2

REFS

Full

0.31

SYSREF± Hold Time from Rising Edge CLK±2

REFH

Full

SYSREF± Setup Time to Rising Edge RFCLK2

REFSRF

Full

0.50

SYSREF± Hold Time from Rising Edge RFCLK2

REFHRF

Full

CLK± Pulse Width High

Divide-by-1 Mode, DCS Enabled

Full

1.8

2.0

2.2

Divide-by-1 Mode, DCS Disabled

Full

1.9

2.0

2.1

Divide-by-2 Mode Through Divide-by-8 Mode

Full

0.8

Aperture Delay

Full

1.0

Aperture Uncertainty (Jitter)

Full

0.16

ps rms

DATA OUTPUT PARAMETERS

Data Output Period or Unit Interval (UI)

Full

L/(20 × M × f

Seconds

Data Output Duty Cycle

25°C

Data Valid Time

25°C

0.78

PLL Lock Time (t

LOCK)

25°C

µs

Wake-Up

Time (Standby)

25°C

µs

Time ADC (Power-Down)3

25°C

250

Time Output (Power-Down)4

25°C

Subclass 0: SYNCINB± Falling Edge to First Valid K.28

Characters (Delay Required for Rx CGS Start)

Full

Multiframes

Subclass 1: SYSREF± Rising Edge to First Valid K.28

Characters (Delay Required for SYNCB± Rising

Edge/Rx CGS Start)

Full

Multiframes

CGS Phase K.28 Characters Duration

Full

Multiframe

Pipeline Delay

JESD204B M1, L1 Mode (Latency)

Full

Cycles5

JESD204B M1, L2 Mode (Latency)

Full

Cycles

JESD204B M2, L1 Mode (Latency)

Full

Cycles

JESD204B M2, L2 Mode (Latency)

Full

Cycles

Additional Pipeline Latency with NSR Enabled

Full

Cycles

Fast Detect (Latency)

Full

Cycles

Data Rate per Lane

25°C

5.0

Gbps

Uncorrelated Bounded High Probability (UBHP) Jitter

25°C

Random Jitter at 5.0 Gbps

25°C

1.7

ps rms

Output Rise/Fall Time

25°C

Differential Termination Resistance

25°C

100

Ω

Out-of-Range Recovery Time

Full

Cycles

1 Conversion rate is the clock rate after the divider.

2 Refer to Figure 3 for timing diagram.

3 Wake-up time ADC is defined as the time required for the ADC to return to normal operation from power-down mode.

4 Wake-up time output is defined as the time required for JESD204B output to return to normal operation from power-down mode.

5 Cycles refers to ADC conversion rate cycles.

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