AD6673 datasheet(32/46 Pages) AD

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Data Sheet

AD6673

Rev. C | Page 31 of 45

8B/10B

ENCODER/

CHARACTER

REPLACEMENT

SERIALIZER

~SYNC

SYSREF

VINA+

(MSB)

(LSB)

VINA–

SERDOUT±

A PATH

ADC

TEST PATTERN

16-BIT

JESD204B

TEST PATTERN

8-BIT

ADC

A13

A12

A11

A10

A11

A12

A13

S10

S11

S12

S13

S14

S15

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

OPTIONAL

SCRAMBLER

1 + x14 + x15

JESD204B

TEST PATTERN

10-BIT

E19

Figure 50. AD6673 Digital Processing of JESD204B Lanes

Table 13. AD6673 JESD204B Typical Configurations

JESD204B

Configure

Setting

M (No. of Converters),

Bits[7:0]

L (No. of Lanes),

Bit 0

F (Octets/Frame),

Bits[7:0], Read Only

S (Samples/ADC/Frame),

Read Only

HD (High Density Mode),

Read Only

0x11

0x12

0x21

0x22 (Default)

DATA

FROM

ADC

FRAME

ASSEMBLER

(ADD TAIL BITS)

OPTIONAL

SCRAMBLER

1 + x14 + x15

8B/10B

ENCODER

RECEIVER

Figure 51. AD6673 ADC Output Data Path

Table 14. AD6673 JESD204B Configuration Using Register 0x3A

Bit

Bit Name

Description

Enable internal

SYSREF± buffer

This bit controls the on-chip buffer for SYSREF±. By default, this bit is 0, which disables the buffer. If the

AD6673 is configured for JESD204B Subclass 1 operation, the SYSREF signal is required to align the JESD204B

link and this bit must be set to 1.

To avoid a false trigger as a result of transients that are caused when enabling the buffer (particularly for one-

shot SYSREF signal configuration), set this bit first and then, in a consecutive SPI register write, configure all

remaining bits in Register 0x3A to the desired JESD204B link configuration, including keeping this bit at 1.

A setting of 0 (default) gates the SYSREF signal so that the internal logic is not affected by an external SYSREF

signal. Set this bit to 0 when in Subclass 0, that is, when the SYSREF signal is not used.

If using Subclass 1 with one-shot SYSREF± mode, enable the buffer while the SYSREF signal is established;

however, it is recommended that the buffer be disabled during normal operation.

If using Subclass 1 with continuous SYSREF± mode, keep the buffer enabled for normal operation.

SYSREF± enable

This bit can be used to enable the circuitry that uses the SYSREF± input signal and must be on to enable

Subclass 1 operation. Set this bit to 1 when using JESD204B Subclass 1 operation.

This bit is self clearing after a valid SYSREF± occurs when the SYSREF± mode bit (Register 0x3A, Bit 2) is set to

1 (configured for one-shot SYSREF± operation).

The SYSREF signal is still used in some digital circuitry even if this bit is 0. To disable the SYSREF± signal

internally, Register 0x3A, Bit 0 must be set to 0.

SYSREF± mode

This bit is used in Subclass 1 operation to define one-shot or continuous SYSREF± mode. To configure

continuous (or gapped periodic) SYSREF± mode, this bit is set to 0. For one-shot operation, this bit is set to 1.

In one-shot mode, it is recommended that the SYSREF buffer be disabled after the SYSREF signal has

occurred by setting Register 0x3A[0] to 0.

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