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FS23 Scheda tecnica(PDF) 127 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 127 Page - NXP Semiconductors |
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127 / 230 page  NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Bit Symbol Description Inhibit V1 low side overcurrent interrupt 0 Interrupt is not inhibited 1 Interrupt is inhibited 0 V1_OCLS_M POR Table 96. M_REG1_MSK register bit description 22.12 M_IO_CTRL Bit 15 14 13 12 11 10 9 8 Write - - - - - - HVIO1HI HVIO1LO Read 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write HVIO2HI HVIO2LO LVIO3HI LVIO3LO LVIO4HI LVIO4LO LVO6HI LVO6LO Read 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Table 97. M_IO_CTRL register bit allocation Bit Symbol Description Request to assert LVO6 when configured as an output 0 No effect (IO remain in its current state) 1 Request to assert LVO6 low 0 LVO6LO POR, self-clear Request to release LVO6 when configured as an output 0 No effect (IO remain in its current state) 1 Request to release LVO6 high 1 LVO6HI POR, self-clear Request to assert LVIO4 when configured as an output 0 No effect (IO remain in its current state) 1 Request to assert LVIO4 low 2 LVIO4LO POR, self-clear Request to release LVIO4 when configured as an output 0 No effect (IO remain in its current state) 1 Request to release LVIO4 high 3 LVIO4HI POR, self-clear Request to assert LVIO3 when configured as an output 0 No effect (IO remain in its current state) 1 Request to assert LVIO3 low 4 LVIO3LO POR, self-clear Request to release LVIO3 when configured as an output 0 No effect (IO remain in its current state) 1 Request to release LVIO3 high 5 LVIO3HI POR, self-clear Table 98. M_IO_CTRL register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 127 / 230 |
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