Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

Preview PDF HTML

FS23 Scheda tecnica(PDF) 130 Page - NXP Semiconductors

Il numero della parte FS23
Spiegazioni elettronici  Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers
PDF  230 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS23 Scheda tecnica(HTML) 130 Page - NXP Semiconductors

Back Button FS23 Datasheet HTML 126Page - NXP Semiconductors FS23 Datasheet HTML 127Page - NXP Semiconductors FS23 Datasheet HTML 128Page - NXP Semiconductors FS23 Datasheet HTML 129Page - NXP Semiconductors FS23 Datasheet HTML 130Page - NXP Semiconductors FS23 Datasheet HTML 131Page - NXP Semiconductors FS23 Datasheet HTML 132Page - NXP Semiconductors FS23 Datasheet HTML 133Page - NXP Semiconductors FS23 Datasheet HTML 134Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 130 / 230 page
background image
NXP Semiconductors
FS23
Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers
Bit
Symbol
Description
Inhibit HVIO1 input state change interrupt
0 Interrupt is not inhibited in Normal mode
1 Interrupt is always inhibited
3
HVIO1_M
POR
Inhibit HVIO2 input state change interrupt
0 Interrupt is not inhibited in Normal mode
1 Interrupt is always inhibited
4
HVIO2_M
POR
Inhibit LVIO3 input state change interrupt
0 Interrupt is not inhibited in Normal mode
1 Interrupt is always inhibited
5
LVIO3_M
POR
Inhibit LVIO4 input state change interrupt
0 Interrupt is not inhibited in Normal mode
1 Interrupt is always inhibited
6
LVIO4_M
POR
Inhibit LVI5 input state change interrupt
0 Interrupt is not inhibited in Normal mode
1 Interrupt is always inhibited
7
LVI5_M
POR
Inhibit LDT event interrupt
0 Interrupt is not inhibited
1 Interrupt is always inhibited
8
LDT_M
POR
Table 102. M_IO_TIMER_MSK register bit description...continued
22.15 M_VSUP_COM_FLG
Bit
15
14
13
12
11
10
9
8
Write[1]
-
-
-
-
VBOS_UV
-
I2C_CRC_I
I2C_REQ_I
Read
0
0
0
VBOS2V1SW_S
VBOS_UV
0
I2C_CRC_I
I2C_REQ_I
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Write[1]
SPI_CRC_I
SPI_CLK_I
SPI_REQ_I
-
VSHS_OV_I
VSHS_UV_I
VSUP_OV_I
VSUP_UV_I
Read
SPI_CRC_I
SPI_CLK_I
SPI_REQ_I
0
VSHS_OV_I
VSHS_UV_I
VSUP_OV_I
VSUP_UV_I
Reset
0
0
0
0
0
0
0
0
Table 103. M_VSUP_COM_FLG register bit allocation
[1]
Write 1 in a flag to clear it.
Bit
Symbol
Description
Report VSUP UV event
0 No VSUP undervoltage event
1 VSUP undervoltage event occurred
0
VSUP_UV_I
POR, or clear on write (write '1')
Table 104. M_VSUP_COM_FLG register bit description
FS23
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 7.0 — 16 October 2024
Document feedback
130 / 230



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Scheda tecnica Scarica

Go To PDF Page


Link URL



Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   Collegamento alla scheda tecnica    |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com