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FS23 Scheda tecnica(PDF) 129 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 129 Page - NXP Semiconductors |
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129 / 230 page  NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Bit Symbol Description Report HVIO2 input state change event if not masked 0 No event on HVIO2 1 Event on HVIO2 occurred 4 HVIO2_I POR, or clear on write (write '1') Report LVIO3 input state change event if not masked 0 No event on LVIO3 1 Event on LVIO3 occurred 5 LVIO3_I POR, or clear on write (write '1') Report LVIO4 input state change event if not masked 0 No event on LVIO4 1 Event on LVIO4 occurred 6 LVIO4_I POR, or clear on write (write '1') Report LVI5 input state change event if not masked 0 No event on LVI5 1 Event on LVI5 occurred 7 LVI5_I POR, or clear on write (write '1') Report LDT event 0 No event on LDT 1 Event on LDT occurred 8 LDT_I POR, or clear on write (write '1') Table 100. M_IO_TIMER_FLG register bit description...continued 22.14 M_IO_TIMER_MSK Bit 15 14 13 12 11 10 9 8 Write - - - - - - - LDT_M Read 0 0 0 0 0 0 0 LDT_M Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write LVI5_M LVIO4_M LVIO3_M HVIO2_M HVIO1_M - WK2_M WK1_M Read LVI5_M LVIO4_M LVIO3_M HVIO2_M HVIO1_M 0 WK2_M WK1_M Reset 0 0 0 0 0 0 0 0 Table 101. M_IO_TIMER_MSK register bit allocation Bit Symbol Description Inhibit WAKE1 input state change interrupt 0 Interrupt is not inhibited in Normal mode 1 Interrupt is always inhibited 0 WK1_M POR Inhibit WAKE2 input state change interrupt 0 Interrupt is not inhibited in Normal mode 1 Interrupt is always inhibited 1 WK2_M POR Table 102. M_IO_TIMER_MSK register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 129 / 230 |
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