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FS23 Scheda tecnica(PDF) 145 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 145 Page - NXP Semiconductors |
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145 / 230 page ![]() NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Bit Symbol Description Configure the PWM2 frequency 0 PWM2 frequency = 200 Hz 1 PWM2 frequency = 400 Hz 10 PWM2_F POR Configure the PWM2 delay time (applies on both edges) 00 PWM2 delay = 0 us 01 PWM2 delay = 5 us 10 PWM2 delay = 10 us 11 PWM2 delay = 15 us 11 to 12 PWM2_DLY POR Table 126. M_PWM2_CFG register bit description...continued 22.27 M_PWM3_CFG Bit 15 14 13 12 11 10 9 8 Write - - - PWM3_DLY PWM3_F PWM3_DC Read 0 0 0 PWM3_DLY PWM3_F PWM3_DC Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write PWM3_DC Read PWM3_DC Reset 0 0 0 0 0 0 0 0 Table 127. M_PWM3_CFG register bit allocation Bit Symbol Description Configure the PWM3 duty cycle PWM3 duty cycle = 100 * PWM3_DC / 1000 0 to 9 PWM3_DC POR Configure the PWM3 frequency 0 PWM3 frequency = 200 Hz 1 PWM3 frequency = 400 Hz 10 PWM3_F POR Configure the PWM3 delay time (applies on both edges) 00 PWM3 delay = 0 us 01 PWM3 delay = 5 us 10 PWM3 delay = 10 us 11 PWM3 delay = 15 us 11 to 12 PWM3_DLY POR Table 128. M_PWM3_CFG register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 145 / 230 |
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