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FS23 Scheda tecnica(PDF) 146 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 146 Page - NXP Semiconductors |
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146 / 230 page ![]() NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers 22.28 M_TIMER_PWM_CTRL Bit 15 14 13 12 11 10 9 8 Write - - - - - - - - Read 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write - TIM1_EN TIM2_EN TIM3_EN - PWM1_EN PWM2_EN PWM3_EN Read 0 TIM1_EN TIM2_EN TIM3_EN 0 PWM1_EN PWM2_EN PWM3_EN Reset 0 0 0 0 0 0 0 0 Table 129. M_TIMER_PWM_CTRL register bit allocation Bit Symbol Description Enable the PWM3 0 PWM3 is disabled 1 PWM3 is enabled 0 PWM3_EN POR, or clear on write (write '1') Enable the PWM2 0 PWM2 is disabled 1 PWM2 is enabled 1 PWM2_EN POR, or clear on write (write '1') Enable the PWM1 0 PWM1 is disabled 1 PWM1 is enabled 2 PWM1_EN POR, or clear on write (write '1') Enable the TIMER3 0 TIMER3 is disabled 1 TIMER3 is enabled 4 TIM3_EN POR, or clear on write (write '1') Enable the TIMER2 0 TIMER2 is disabled 1 TIMER2 is enabled 5 TIM2_EN POR, or clear on write (write '1') Enable the TIMER1 0 TIMER1 is disabled 1 TIMER1 is enabled 6 TIM1_EN POR, or clear on write (write '1') Table 130. M_TIMER_PWM_CTRL register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 146 / 230 |
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