H8SSLASH2224 datasheet(414/1071 Pages) RENESAS

414 / 1071 page

Section 10 I/O Ports

Rev. 5.00 Aug 08, 2006 page 328 of 982

REJ09B0054-0500

10.6

Port A

Port A is a 4-bit I/O port and has the following register.

• Port A data direction register (PADDR)

• Port A data register (PADR)

• Port A register (PORTA)

• Port A pull-up MOS control register (PAPCR)

• Port A open drain control register (PAODR)

10.6.1

Port A Data Direction Register (PADDR)

PADDR specifies input or output the port A pins using the individual bits. PADDR cannot be

read; if it is, an undefined value will be read. This register is a write-only register, and cannot be

written by bit manipulation instruction. For details, see section 2.9.4, Access Methods for

Registers with Write-Only Bits.

Bit

Bit Name

Initial Value

R/W

Description

7 to 4

—

Undefined

—

Reserved

These bits are always read as undefined value.

PA3DDR

PA2DDR

PA1DDR

PA0DDR

When a pin is specified as a general purpose I/O

port, setting this bit to 1 makes the corresponding

port A pin an output pin. Clearing this bit to 0 makes

the pin an input pin.

10.6.2

Port A Data Register (PADR)

PADR stores output data for port A pins.

Bit

Bit Name

Initial Value

R/W

Description

7 to 4

—

Undefined

—

Reserved

These bits are always read as undefined value.

PA3DR

R/W

PA2DR

R/W

PA1DR

R/W

PA0DR

0R/W

Output data for a pin is stored when the pin is

specified as a general purpose I/O port.

H8S/2224 Scheda tecnica(PDF) 414 Page - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 414 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL