H8SSLASH2224 datasheet(415/1071 Pages) RENESAS

415 / 1071 page

Section 10 I/O Ports

Rev. 5.00 Aug 08, 2006 page 329 of 982

REJ09B0054-0500

10.6.3

Port A Register (PORTA)

PORTA shows the pin states. This register cannot be modified.

Bit

Bit Name

Initial Value

R/W

Description

7 to 4

—

Undefined

—

Reserved

These bits are always read as undefined value.

PA3

—*

PA2

—*

PA1

—*

PA0

—*

If this bit is read while PADDR is set to 1, the PADR

value is read. If this bit is read while PADDR is

cleared, the PA3 pin states are read.

Note:

* Determined by the states of PA3 to PA0 pins.

10.6.4

Port A Pull-Up MOS Control Register (PAPCR)

PAPCR controls the on/off state of port A input pull-up MOS.

Bit

Bit Name

Initial Value

R/W

Description

7 to 4

—

Undefined

—

Reserved

These bits are always read as undefined value.

PA3PCR

R/W

PA2PCR

R/W

PA1PCR

R/W

PA0PCR

R/W

When the pin is specified as an input port, setting the

corresponding bit to 1 turns on the input pull-up MOS

for that pin.

10.6.5

Port A Open Drain Control Register (PAODR)

PAODR selects output state of port A.

Bit

Bit Name

Initial Value

R/W

Description

7 to 4

—

Undefined

—

Reserved

These bits are always read as undefined value.

PAODR

R/W

PAODR

R/W

PAODR

R/W

PAODR

R/W

When this bit is set to 1, the corresponding port A pin

functions as open drain output. When this bit is

cleared to 0, the corresponding pin functions as

CMOS output.

H8S/2224 Scheda tecnica(PDF) 415 Page - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 415 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL