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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2224 Scheda tecnica(PDF) 552 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 552 Page - Renesas Technology Corp |
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552 / 1071 page  Section 13 Watchdog Timer (WDT) Rev. 5.00 Aug 08, 2006 page 466 of 982 REJ09B0054-0500 Overflow Interrupt control WOVI (interrupt request signal) Internal reset signal*1 Reset control RSTCSR TCNT_0 TCSR_0 φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Clock Clock select Internal clock sources Bus interface Module bus TCSR_0: TCNT_0: RSTCSR: Notes: 1. The type of internal reset signal depends on a register setting. The power-on reset or manual reset can be selected as the internal reset. 2. When a sub-clock is operating in power-down mode, φ will be φ SUB. Timer control/status register0 Timer counter0 Reset control/status register WDT Legend: *2 Figure 13.1 Block Diagram of WDT_0 (1) |
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