H8SSLASH2224 datasheet(553/1071 Pages) RENESAS

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Section 13 Watchdog Timer (WDT)

Rev. 5.00 Aug 08, 2006 page 467 of 982

REJ09B0054-0500

Overflow

Interrupt

control

WOVI

(interrupt request

signal)

Internal NMI

(interrupt request signal)

Internal reset signal*

Reset

control

TCNT_1

TCSR_1

φ/2

φ/64

φ/128

φ/512

φ/2048

φ/8192

φ/32768

φ/131072

φSUB/2

φSUB/4

φSUB/8

φSUB/16

φSUB/32

φSUB/64

φSUB/128

φSUB/256

Clock

select

Internal clock

sources

Bus

interface

Module bus

WDT

TCSR_1:

TCNT_1:

Note: * The type of internal reset signal depends on a register setting.

Caused reset is the power-on reset.

Timer control/status register1

Timer counter1

Legend:

BUZZ

Figure 13.1 Block Diagram of WDT_1 (2)

13.2

Input/Output Pins

Table 13.1 Pin Configuration

Name

Symbol

I/O

Function

Buzzer Output

BUZZ

Output

Output the clock selected by WDT_1

13.3

The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and

RSTCSR have to be written to by a different method to normal registers. For details, refer to

section 13.6.1, Notes on Register Access. For details on the system control register and pin

function control register, refer to section 3.2.2, System Control Register (SYSCR) and section

7.3.6, Pin Function Control Register (PFCR), respectively.

• Timer counter (TCNT)

• Timer control/status register (TCSR)

• Reset control/status register (RSTCSR)

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