H8SSLASH2224 datasheet(551/1071 Pages) RENESAS

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Section 13 Watchdog Timer (WDT)

Rev. 5.00 Aug 08, 2006 page 465 of 982

REJ09B0054-0500

Section 13 Watchdog Timer (WDT)

The watchdog timer (WDT) is an 8-bit timer that can generate an internal reset signal for this LSI

if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.

When this watchdog function is not needed, the WDT can be used as an interval timer. In interval

timer operation, an interval timer interrupt is generated each time the counter overflows.

The block diagram of the WDT is shown in figure 13.1.

13.1

Features

• Selectable from 8 counter input clocks for WDT_0

Selectable from 16 counter input clocks for WDT_1

• Switchable between watchdog timer mode and interval timer mode

In watchdog timer mode

• Choosable between power-on reset or manual reset as internal reset

• If the counter in WDT_0 overflows, it is possible to select whether this LSI is internally reset

or not

• If the counter in WDT_1 overflows, it is possible to select whether this LSI is internally reset

or the internal NMI interrupt is generated

In interval timer mode

• If the counter overflows, the WDT generates an interval timer interrupt (WOVI)

• The selected clock can be output from the BUZZ output pin (WDT_1)

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