H8SSLASH2224 datasheet(554/1071 Pages) RENESAS

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Section 13 Watchdog Timer (WDT)

Rev. 5.00 Aug 08, 2006 page 468 of 982

REJ09B0054-0500

13.3.1

Timer Counter (TCNT)

TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in

TCSR is cleared to 0.

13.3.2 Timer Control/Status Register (TCSR)

TCSR functions include selecting the clock source to be input to TCNT and the timer mode.

• TCSR_0

Bit

Bit Name

Initial

Value

R/W

Description

7OVF

R/(W)*

Overflow Flag

Indicates that TCNT has overflowed. Only a 0 can

be written to this bit, to clear the flag.

[Setting condition]

When TCNT overflows (changes from H'FF to

H'00)

When internal reset request generation is selected

in watchdog timer mode, OVF is cleared

automatically by the internal reset.

[Clearing condition]

Cleared by reading TCSR*

2 when OVF = 1, then

writing 0 to OVF

6WT/

R/W

Timer Mode Select

Selects whether the WDT is used as a watchdog

timer or interval timer.

0: Interval timer mode (an interval timer interrupt

(WOVI) is requested to CPU)

1: Watchdog timer mode (internal reset selectable)

TME

R/W

Timer Enable

When this bit is set to 1, TCNT starts counting.

When this bit is cleared, TCNT stops counting and

is initialized to H'00.

4, 3



All 1



Reserved

These bits are always read as 1 and cannot be

modified.

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