H8SSLASH2224 datasheet(556/1071 Pages) RENESAS

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Section 13 Watchdog Timer (WDT)

Rev. 5.00 Aug 08, 2006 page 470 of 982

REJ09B0054-0500

• TCSR_1

Bit

Bit Name

Initial

Value

R/W

Description

7OVF

R/(W)

Overflow Flag

Indicates that TCNT has overflowed. Only a 0 can

be written to this bit, to clear the flag.

[Setting condition]

When TCNT overflows (changes from H'FF to

H'00)

When internal reset request generation is selected

in watchdog timer mode, OVF is cleared

automatically by the internal reset.

[Clearing condition]

Cleared by reading TCSR*

2 when OVF = 1, then

writing 0 to OVF

6WT/

R/W

Timer Mode Select

Selects whether the WDT is used as a watchdog

timer or interval timer.

0: Interval timer mode (an interval timer interrupt

(WOVI) is requested to CPU)

1: Watchdog timer mode (a power-on reset or NMI

interrupt is requested to CPU)

TME

R/W

Timer Enable

When this bit is set to 1, TCNT starts counting.

When this bit is cleared, TCNT stops counting and

is initialized to H'00.

PSS

R/W

Prescaler Select

Selects the clock source input to TCNT of WDT_1

0: TCNT counts divided clock of

φ-base prescaler

(PSM)

1: TCNT counts divided clock of

φSUB-base

prescaler (PSS)

3RST/

NMI

R/W

Reset or NMI (RST/

NMI)

When TCNT overflows in watchdog timer mode,

either a power-on reset or NMI interrupt is

selected.

0: An NMI interrupt is requested

1: Reset is requested

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