H8SSLASH2224 datasheet(639/1071 Pages) RENESAS

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Section 15 Serial Communication Interface (SCI)

Rev. 5.00 Aug 08, 2006 page 553 of 982

REJ09B0054-0500

15.3.4

Transmit Shift Register (TSR)

TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first

transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be

directly accessed by the CPU.

15.3.5

Serial Mode Register (SMR)

SMR is used to set the SCI’s serial transfer format and select the baud rate generator clock source.

Some bit functions of SMR differ between normal serial communication interface mode and Smart

Card interface mode.

• Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)

Bit

Bit Name

Initial

Value

R/W

Description

7C/

R/W

Communication Mode

0: Asynchronous mode

1: Clocked synchronous mode

CHR

R/W

Character Length (enabled only in asynchronous

mode)

0: Selects 8 bits as the data length.

1: Selects 7 bits as the data length. LSB-first is

fixed and the MSB (bit 7) of TDR is not

transmitted in transmission.

In clocked synchronous mode, a fixed data length

of 8 bits is used.

R/W

Parity Enable (enabled only in asynchronous

mode)

When this bit is set to 1, the parity bit is added to

transmit data before transmission, and the parity

bit is checked in reception. For a multiprocessor

format, parity bit addition and checking are not

performed regardless of the PE bit setting.

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