H8SSLASH2224 datasheet(643/1071 Pages) RENESAS

643 / 1071 page

Section 15 Serial Communication Interface (SCI)

Rev. 5.00 Aug 08, 2006 page 557 of 982

REJ09B0054-0500

Bit

Bit Name

Initial

Value

R/W

Description

BCP1

BCP0

R/W

Base Clock Pulse 0 and 1

These bits specify the number of base clock

periods in a 1-bit transfer interval on the Smart

Card interface.

00: 32 clock (S = 32)

01: 64 clock (S = 64)

10: 372 clock (S = 372)

11: 256 clock (S = 256)

For details, refer to section 15.7.4, Receive Data

Sampling Timing and Reception Margin. S stands

for the value of S in BRR (see section 15.3.9, Bit

Rate Register (BRR)).

CKS1

CKS0

R/W

Clock Select 0 and 1

These bits select the clock source for the baud rate

generator.

00:

φ clock (n = 0)

01:

φ/4 clock (n = 1)

10:

φ/16 clock (n = 2)

11:

φ/64 clock (n = 3)

For the relationship between the bit rate register

setting and the baud rate, see section 15.3.9, Bit

Rate Register (BRR). n is the decimal

representation of the value of n in BRR (see

section 15.3.9, Bit Rate Register (BRR)).

Note: etu (Elementary Time Unit): Time for transfer of 1 bit

15.3.6

Serial Control Register (SCR)

SCR is a register that enables or disables SCI transfer operations and interrupt requests, and is also

used to selection of the transfer clock source. For details on interrupt requests, refer to section

15.9, Interrupt Sources. Some bit functions of SCR differ between normal serial communication

interface mode and Smart Card interface mode.

H8S/2224 Scheda tecnica(PDF) 643 Page - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 643 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL