H8SSLASH2224 datasheet(641/1071 Pages) RENESAS

641 / 1071 page

Section 15 Serial Communication Interface (SCI)

Rev. 5.00 Aug 08, 2006 page 555 of 982

REJ09B0054-0500

Bit

Bit Name

Initial

Value

R/W

Description

CKS1

CKS0

R/W

Clock Select 0 and 1

These bits select the clock source for the baud rate

generator.

00:

φ clock (n = 0)

01:

φ/4 clock (n = 1)

10:

φ/16 clock (n = 2)

11:

φ/64 clock (n = 3)

For the relationship between the bit rate register

setting and the baud rate, see section 15.3.9, Bit

Rate Register (BRR). n is the decimal

representation of the value of n in BRR (see

section 15.3.9, Bit Rate Register (BRR)).

• Smart Card Interface Mode (When SMIF in SCMR is 1)

Bit

Bit Name

Initial

Value

R/W

Description

R/W

GSM Mode

When this bit is set to 1, the SCI operates in GSM

mode. In GSM mode, the timing of the TEND

setting is advanced by 11.0 etu (Elementary Time

Unit: the time for transfer of 1 bit), and clock output

control mode addition is performed. For details,

refer to section 15.7.8, Clock Output Control.

0: Normal smart card interface mode operation

(initial value)

• The TEND flag is generated 12.5 etu (11.5 etu

in the block transfer mode) after the beginning

of the start bit.

• Clock output on/off control only

1: GSM mode operation in smart card interface

mode

• The TEND flag is generated 11.0 etu after the

beginning of the start bit.

• In addition to clock output on/off control,

high/low fixed control is supported (set using

SCR).

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