H8SSLASH2224 datasheet(642/1071 Pages) RENESAS

642 / 1071 page

Section 15 Serial Communication Interface (SCI)

Rev. 5.00 Aug 08, 2006 page 556 of 982

REJ09B0054-0500

Bit

Bit Name

Initial

Value

R/W

Description

BLK

R/W

When this bit is set to 1, the SCI operates in block

transfer mode. For details on block transfer mode,

refer to section 15.7.3, Block Transfer Mode.

0: Normal smart card interface mode operation

(initial value)

• Error signal transmission, detection, and

automatic data retransmission are performed.

• The TXI interrupt is generated by the TEND

flag.

• The TEND flag is set 12.5 etu (11.0 etu in the

GSM mode) after transmission starts.

1: Operation in block transfer mode

• Error signal transmission, detection, and

automatic data retransmission are not

performed.

• The TXI interrupt is generated by the TDRE

flag.

• The TEND flag is set 11.5 etu (11.0 etu in the

GSM mode) after transmission starts.

R/W

Parity Enable (enabled only in asynchronous

mode)

When this bit is set to 1, the parity bit is added to

transmit data in transmission, and the parity bit is

checked in reception. In Smart Card interface

mode, this bit must be set to 1.

4O/

R/W

Parity Mode (enabled only when the PE bit is 1 in

asynchronous mode)

0: Selects even parity.

1: Selects odd parity.

For details on setting this bit in Smart Card

interface mode, refer to section 15.7.2, Data

Format (Except for Block Transfer Mode).

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