H8SSLASH2224 datasheet(644/1071 Pages) RENESAS

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Section 15 Serial Communication Interface (SCI)

Rev. 5.00 Aug 08, 2006 page 558 of 982

REJ09B0054-0500

• Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)

Bit

Bit Name

Initial

Value

R/W

Description

TIE

R/W

Transmit Interrupt Enable

When this bit is set to 1, the TXI interrupt request is

enabled.

TXI interrupt request cancellation can be

performed by reading 1 from the TDRE flag in

SSR, then clearing it to 0, or clearing the TIE bit to

RIE

R/W

Receive Interrupt Enable

When this bit is set to 1, RXI and ERI interrupt

requests are enabled.

RXI and ERI interrupt request cancellation can be

performed by reading 1 from the RDRF, FER,

PER, or ORER flag in SSR, then clearing the flag

to 0, or clearing the RIE bit to 0.

R/W

Transmit Enable

When this bit s set to 1, transmission is enabled.

In this state, serial transmission is started when

transmit data is written to TDR and the TDRE flag

in SSR is cleared to 0.

SMR setting must be performed to decide the

transfer format before setting the TE bit to 1. When

this bit is cleared to 0, the transmission operation is

disabled, and the TDRE flag is fixed at 1.

R/W

Receive Enable

When this bit is set to 1, reception is enabled.

Serial reception is started in this state when a start

bit is detected in asynchronous mode or serial

clock input is detected in clocked synchronous

mode.

SMR setting must be performed to decide the

reception format before setting the RE bit to 1.

Clearing the RE bit to 0 does not affect the RDRF,

FER, and ORER flags, which retain their states.

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