H8SSLASH2224 datasheet(312/1071 Pages) RENESAS

Il numero della parte	H8S/2224

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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312 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 226 of 982

REJ09B0054-0500

Bit

Bit Name

Initial Value

R/W

Description

DTME0

R/W

Data Transfer Master Enable 0

Together with the DTE0 bit, this bit controls

enabling or disabling of data transfer on

channel 0. When both the DTME0 bit and DTE0

bit are set to 1, transfer is enabled for channel

If channel 0 is in the middle of a burst mode

transfer when an NMI interrupt is generated, the

DTME0 bit is cleared, the transfer is interrupted,

and bus mastership passes to the CPU. When

the DTME0 bit is subsequently set to 1 again,

the interrupted transfer is resumed. In block

transfer mode, however, the DTME0 bit is not

cleared by an NMI interrupt, and transfer is not

interrupted.

0: Data transfer is disabled

1: Data transfer is enabled

[Clearing conditions]

• When initialization is performed

• When NMI is input in burst mode

• When 0 is written to the DTME0 bit

[Setting condition]

When 1 is written to DTME0 after reading

DTME0 = 0

H8S/2224 Scheda tecnica(PDF) 312 Page - Renesas Technology Corp