H8SSLASH2224 datasheet(313/1071 Pages) RENESAS

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Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 227 of 982

REJ09B0054-0500

Bit

Bit Name

Initial Value

R/W

Description

DTE0

R/W

Data Transfer Enable 0

Enables or disables DMA transfer for the

activation source selected by the DTF3 to DTF0

bits in DMACR of channel 0.

When DTE0 = 0, data transfer is disabled and

the activation source is ignored. If the activation

source is an internal interrupt, an interrupt

request is issued to the CPU or DTC. If the

DTE0 bit is cleared to 0 when DTIE0 = 1, the

DMAC regards this as indicating the end of a

transfer, and issues a transfer end interrupt

request to the CPU.

When DTE0 = 1 and DTME0 = 1, data transfer

is enabled and the DMAC waits for a request by

the activation source. When a request is issued

by the activation source, DMA transfer is

executed.

0: Data transfer is disabled

1: Data transfer is enabled

[Clearing conditions]

• When initialization is performed

• When the specified number of transfers

have been completed

• When 0 is written to the DTE0 bit to forcibly

suspend the transfer, or for a similar reason

[Setting condition]

When 1 is written to the DTE0 bit after reading

DTE0 = 0

DTIE1B

R/W

Data Transfer Interrupt Enable 1B

Enables or disables an interrupt to the CPU or

DTC when transfer on channel 1 is interrupted.

If the DTME1 bit is cleared to 0 when DTIE1B =

1, the DMAC regards this as indicating a break

in the transfer, and issues a transfer break

interrupt request to the CPU or DTC.

A transfer break interrupt can be canceled

either by clearing the DTIE1B bit to 0 in the

interrupt handling routine, or by performing

processing to continue transfer by setting the

DTME1 bit to 1.

0: Data transfer is disabled

1: Data transfer is enabled

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