H8SSLASH2224 datasheet(314/1071 Pages) RENESAS

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Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 228 of 982

REJ09B0054-0500

Bit

Bit Name

Initial Value

R/W

Description

DTIE1A

R/W

Data Transfer End Interrupt Enable 1A

Enables or disables an interrupt to the CPU or

DTC when transfer ends. If the DTE1 bit is

cleared to 1 when DTIE1A = 1, the DMAC

regards this as indicating the end of a transfer,

and issues a transfer end interrupt request to

the CPU or DTC.

A transfer end interrupt can be canceled either

by clearing the DTIE1A bit to 0 in the interrupt

handling routine, or by performing processing to

continue transfer by setting the transfer counter

and address register again, and then setting the

DTE1 bit to 1.

0: Data transfer is disabled

1: Data transfer is enabled

DTIE0B

R/W

Data Transfer Interrupt Enable 0B

Enables or disables an interrupt to the CPU or

DTC when transfer on channel 1 is interrupted.

If the DTME0 bit is cleared to 0 when DTIE0B =

1, the DMAC regards this as indicating a break

in the transfer, and issues a transfer break

interrupt request to the CPU or DTC.

A transfer break interrupt can be canceled

either by clearing the DTIE0B bit to 0 in the

interrupt handling routine, or by performing

processing to continue transfer by setting the

DTME0 bit to 1.

0: Data transfer is disabled

1: Data transfer is enabled

DTIE0A

R/W

Data Transfer End Interrupt Enable 0A

Enables or disables an interrupt to the CPU or

DTC when transfer ends. If the DTE0 bit is

cleared to 0 when DTIE0A = 1, the DMAC

regards this as indicating the end of a transfer,

and issues a transfer end interrupt request to

the CPU or DTC.

A transfer end interrupt can be canceled either

by clearing the DTIE0A bit to 0 in the interrupt

handling routine, or by performing processing to

continue transfer by setting the transfer counter

and address register again, and then setting the

DTE0 bit to 1.

0: Data transfer is disabled

1: Data transfer is enabled

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