H8SSLASH2224 datasheet(315/1071 Pages) RENESAS

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Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 229 of 982

REJ09B0054-0500

8.3.6

DMA Write Enable Register (DMAWER)

The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the

transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies

restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for

the specific channel, to prevent inadvertent rewriting of registers other than those for the channel

concerned. The restrictions applied by DMAWER are valid for the DTC.

Bit

Bit Name

Initial Value

R/W

Description

7 to 4



All 0

−

Reserved

These bits are always read as 0 and cannot be

modified.

WE1B

R/W

Write Enable 1B

Enables or disables writes to all bits in

DMACR1B, bits 11, 7, and 3 in DMABCR, and

bit 5 in DMATCR.

0: Writes are disabled

1: Writes are enabled

WE1A

R/W

Write Enable 1A

Enables or disables writes to all bits in

DMACR1A, and bits 10, 6, and 2 in DMABCR.

0: Writes are disabled

1: Writes are enabled

WE0B

R/W

Write Enable 0B

Enables or disables writes to all bits in

DMACR0B, bits 9, 5, and 1 in DMABCR, and bit

4 in DMATCR.

0: Writes are disabled

1: Writes are enabled

WE0A

R/W

Write Enable 0A

Enables or disables writes to all bits in

DMACR0A, and bits 8, 4, and 0 in DMABCR.

0: Writes are disabled

1: Writes are enabled

Figure 8.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt

request, and reactivating channel 0A. The address register and count register areas are set again

during the first DTC transfer, then the control register area is set again during the second DTC

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